1. Field of the Invention
The present invention relates to a semiconductor device which incorporates a chip-size semiconductor package, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
For example, in a semiconductor device called BGA (Ball Grid Array), a semiconductor chip formed with an LSI and the like is mounted on the upper center surface of a relay board (interposer) slightly larger in size than the semiconductor chip. Connection terminals of solder balls are arrayed in a matrix on the lower surface of the relay board. The relay board is used to sufficiently increase the size and pitch by a distribution wire in order to ensure connection strength and reliability in bonding an external connection electrode formed on the semiconductor chip to another circuit board.
FIG. 84 is a sectional view showing an example of a conventional semiconductor device. A semiconductor chip 1 has a structure in which a plurality of bump electrodes 3 of copper or the like are arranged at the periphery on the lower surface of a silicon substrate 2.
A relay board 4 has a base film 5 slightly larger in size than the silicon substrate 2 of the semiconductor chip 1. Distribution wires 6 which are respectively connected to the bump electrodes 3 of the semiconductor chip 1 are formed on the upper surface of the base film 5.
The distribution wires 6 are comprised of first connection pads 7 which are arranged in correspondence with the bump electrodes 3 of the semiconductor chip 1, second connection pads 8 which are arrayed in a matrix, and lead lines 9 which connect the first and second connection pads 7 and 8. Circular holes 10 are formed in the base film 5 at portions corresponding to the centers of the second connection pads 8.
The semiconductor chip 1 is mounted on the upper center surface of the relay board 4 via an anisotropic conductive adhesive 11. The anisotropic conductive adhesive 11 is prepared by adding many conductive particles 13 into a thermosetting resin 12.
When the semiconductor chip 1 is to be mounted on the relay board 4, the semiconductor chip 1 is aligned and simply placed on the upper center surface of the relay board 4 via the sheet-like anisotropic conductive adhesive 11.
A predetermined pressure is applied for bonding at a temperature at which the thermosetting resin 12 sets. The bump electrodes 3 then push away the thermosetting resin 12 and are electrically connected to the upper surfaces of the first connection pads 7 via the conductive particles 13. In addition, the lower surface of the semiconductor chip 1 is adhered to the upper surface of the relay board 4 via the thermosetting resin 12.
A resin sealing film 14 made of an epoxy resin is formed on the entire upper surface of the relay board 4 including the semiconductor chip 1. Solder balls 15 are formed in the circular holes 10, and connected to the lower surfaces of the second connection pads 8. Since the second connection pads 8 are arrayed in a matrix, the solder halls 15 are also arrayed in a matrix.
The solder ball 15 is larger in size than the bump electrode 3 of the semiconductor chip 1. In order to avoid contact between the solder balls 15, their arrangement interval must be larger than that of the bump electrodes 3. When the number of bump electrodes 3 of the semiconductor chip 1 increases, the arrangement region of the solder balls 15 must be set larger than the size of the semiconductor chip 1 in order to obtain an arrangement interval necessary for the solder balls 15. For this purpose, the relay board 4 is designed slightly larger in size than the semiconductor chip 1. Of the solder balls 15 arrayed in a matrix, peripheral solder balls 15 are arranged around the semiconductor chip 1.
The conventional semiconductor device adopts the relay board 4 having the distribution wire 6. By bonding after alignment, the lower surface of the bump electrode 3 of the semiconductor chip 1 is electrically connected to the upper surface of the first connection pad 7 of the distribution wire 6 on the relay board 4 via the conductive particles 13 of the anisotropic conductive adhesive 11. If the number of bump electrodes 3 of the semiconductor chip 1 increases and the size and arrangement interval of the bump electrodes 3 decrease, alignment becomes very difficult. By increasing the size of the semiconductor chip 1, the size and arrangement interval of the bump electrodes 3 can be increased. However, the number of semiconductor chips which can be formed from a wafer greatly decreases, resulting in an expensive semiconductor chip. The semiconductor chips 1 must be bonded and mounted on the relay board 4 one by one, which makes the manufacturing process cumbersome. This also applies to a multi-chip module type semiconductor device having a plurality of semiconductor chips.